Delay-locked loops (DLLs) are typically used to generate multi-phase clock signals from a single phase clock input. DLLs typically include delay line composed of identical delay cells. The input signal and its delayed version are compared by a phase detector. The phase error is used to adjust the delay line until the signals at the phase detector input are aligned. Once the signals are aligned, the total delay of the delay line is equal to one input clock period. If N delay cells are used in the delay line, N phases of the input clock will be available, one at the output of each delay cell.
Digital DLL architectures address various challenges of analog implementations such as, difficulties introduced by charge pump design, charge leakage for the capacitor, flicker noise in the charge pump current, etc. However, performance of the digital DLLs may be compromised by drift in the delay provided by the delay line.